Field of the Invention
The invention relates to a system and a method for the functional testing of a semiconductor memory chip, in particular of a DRAM or SGRAM chip which can be operated in the DDR mode, in which the memory cells are subdivided into a plurality of spatially separate memory blocks.
In order to keep up with the rising requirements with regard to bandwidths and volumes of data in the information industry, DRAM or SGRAM memories with ever higher data rates or clock frequencies must be developed. In the field of graphics, clock frequencies of 400 MHz and a resultant data rate (double data rate) of 800 Mbits/s have been attained in the meantime, with further increases in the clock frequencies being expected. Even the most modern test units (memory testers) no longer have the accuracy and speed to test the interfaces of future products with even higher data rates, which interfaces write and read out data with such high clock frequencies. The limit of the data rate is primarily determined by the data path synchronization and the limiting parameters of the input and output stages of the data lines, that is to say by the memory interface. By contrast, the speed in the core, that is to say in the memory cells and the sense amplifiers, scarcely increases through the use of a higher “prefetch”.
In the prior art, the interface of the memory chips is still measured by very fast and expensive memory testers. The costs for such test units are very high and are manifested to an ever greater extent in the production costs of the memory chips. At the ever increasing clock frequencies, the speed limit of the tester hardware is often already being approached and it is necessary to accept a loss of yield on account of measurement inaccuracies. Moreover, at high speeds the tester can no longer evaluate all the data. On account of these limitations, an interface test that reflects the conditions in the later application is no longer possible.
For the forthcoming generation of very fast memories, to date there is as yet no method that allows the testing of the interface at maximum module speed.